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data sheet ics854110aki revision b january 27, 2011 1 ?2011 integrated device technology, inc. 2.5v differential lvds clock buffer ICS854110I general description the ICS854110I is a high-performance differential lvds clock fanout buffer. the device is designed for signal fanout of high-frequency, low phase-noise clock signals. the selected differential input signal is distributed to ten differential lvds outputs. the ICS854110I is characterized to operate from a 2.5v power supply. guaranteed output-to-output and part-to-part skew characteristics make the ICS854110I ideal for those clock distribution applications demanding well-defined performance and repeat ability. the device offers an output slew rate control with four pre-set output transition times to solve crosstalk and emi problems in complex board designs. a fail-safe input design forces t he outputs to a defined state if differential clock inputs are open or shorted, see table 3d. features ? two differential input reference clocks ? differential pair can accept the following differential input levels: lv p e c l , lv d s ? ten lvds outputs ? maximum clock frequency: 200mhz ? output slew rate control ? fail-safe differential inputs ? lvcmos interface levels for all control inputs ? output skew: 260ps (maximum), for fastest slew rate setting of 0.650 v/ns ? part-to-part skew: 1.2ns (maximum) ? full 2.5v supply voltage ? lead-free (rohs 6) 32-lead vfqfn and 32-lead lqfp package ? -40c to 85c ambient operating temperature 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 iset clk_sel clk0 nclk0 gnd clk1 nclk1 noe q3 nq3 q4 nq4 q5 nq5 q6 nq6 gnd nq9 q9 nq8 q8 nq7 q7 v dd q0 nq0 q1 nq1 q2 nq2 gnd v dd 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 iset clk_sel clk0 nclk0 gnd clk1 nclk1 noe q3 nq3 q4 nq4 q5 nq5 q6 nq6 gnd nq9 q9 nq8 q8 nq7 q7 v dd q0 nq0 q1 nq1 q2 nq2 gnd v dd f ref clk0 nclk0 clk1 nclk1 clk_sel iset noe pulldown q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 q8 nq8 q9 nq9 0 1 slew-rate control r set pulldown gnd block diagram pin assignments 854110aki 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package to p v i e w 854110ayi 32-lead lqfp 7mm x 7mm x 1.4mm package body y package to p v i e w
ics854110aki revision b january 27, 2011 2 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer table 1. pin descriptions note: pulldown refers to an internal input resistor. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 iset an external fixed resistor (rset) from this pin to ground is needed to provide a reference current for setting the slew rate of the differential outputs q[0:9], nq[0:9]. see table 3c for function. 2 clk_sel input pulldown input clock select. see table 3a for fu nction. lvcmos/lvttl interface levels. 3 clk0 input non-inverting clock/data input 0. 4 nclk0 input inverting differential clock input 0. 5, 9, 25 gnd power power supply ground. 6 clk1 input non-inverting clock/data input 1. 7 nclk1 input inverting differential clock input 1. 8 noe input pulldown output enable. see table 3b for func tion. lvcmos/lvttl interface levels. 10, 11 nq9, q9 output differential output pair 9. lvds interface levels. 12, 13 nq8, q8 output differential output pair 8. lvds interface levels. 14, 15 nq7, q7 output differential output pair 7. lvds interface levels. 16, 32 v dd power power supply pins. 17, 18 nq6, q6 output differential output pair 6. lvds interface levels. 19, 20 nq5, q5 output differential output pair 5. lvds interface levels. 21, 22 nq4, q4 output differential output pair 4. lvds interface levels. 23, 24 nq3, q3 output differential output pair 3. lvds interface levels. 26, 27 nq2, q2 output differential output pair 2. lvds interface levels. 28, 29 nq1, q1 output differential output pair 1. lvds interface levels. 30, 31 nq0, q0 output differential output pair 0. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k ?
ics854110aki revision b january 27, 2011 3 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer function tables table 3a. clk_sel configuration table note: clk_sel is an asynchronous control. table 3b. noe configuration table note: oe is an asynchronous control. table 3c. r set configuration table note: the rset resistor at the iset pin allows configuration of the outputs to one of four pre-set output slew rates. a 5% variation of the rset resistor size will be tolerated. note: slew rates are defined as 100mv from the center of q ? nq signal. table 3d. guaranteed input fail safe operations for clk0, nclk0 and clk1, nclk1 input operation clk_sel 0 clk0, nclk0 is the selected reference clock 1 clk1, nclk1 is the selected reference clock input operation noe 0 outputs qx, nqx are enabled. 1 outputs qx, nqx are in high-impedance state. r set typical output slew rate (v/ns) resistor size (k ? ) 4 0.650 (fastest) 15 0.170 50 0.150 150 0.115 (slowest) input state of selected input outputs q[0:9], nq[0:9] logic low (selected input: clkx = low, nclk x = high) logic low (qx = low, nqx = high) logic high (selected input: clkx = high, nc lkx = low) logic high (qx = high, nqx = low) inputs open (selected input: clkx = open, nclkx = open) logic high (qx = high, nqx = low) inputs shorted (selected input: clkx shorted to nclkx and tied to v dd ) logic high (qx = high, nqx = low) input shorted (selected input: clkx shorted to nclkx and floating) logic high (qx = high, nqx = low)
ics854110aki revision b january 27, 2011 4 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl input dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuos current surge current 10ma 15ma package thermal impedance, ja 32 lead vfqfn 32 lead lqfp 37.0c/w (0 mps) 65.7c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v i dd power supply current no load, r set not connected 18 ma all outputs loaded, r set = 4k ? 86 ma no load, r set = 4k ? 30 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_sel, noe v dd = v in = 2.625v 150 a i il input low current clk_sel, noe v dd = 2.625v, v in = 0v -5 a symbol parameter test conditi ons minimum typical maximum units v pp peak-to-peak input voltage; note 1 0.15 1.2 v v cmr common mode input voltage; note 1, 2 gnd + 0.8 v dd - 0.85 v
ics854110aki revision b january 27, 2011 5 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac electrical characteristics, v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v od differential output voltage r set = 4k ? 250 600 mv ? v od v od magnitude change r set = 4k ? 50 mv v os offset voltage r set = 4k ? 1.115 1.430 v ? v os v os magnitude change r set = 4k ? 50 mv symbol parameter test conditio ns minimum typical maximum units f ref input frequency r set = 4k ? 200 mhz r set = 15k ? 30 mhz r set = 50k ? 20 mhz r set = 150k ? 16 mhz f out output frequency q[9:0], nq[9:0] r set = 4k ? 200 mhz r set = 15k ? 30 mhz r set = 50k ? 20 mhz r set = 150k ? 16 mhz t jit buffer additive phase jitter, rms; refer to additive phase jitter section r set = 4k ?, f ref = 125mhz, integration range: 12khz ? 20mhz 0.291 ps t pd propagation delay; note 1 clkx, nclkx to any qx, nqx output r set = 4k ? 3.2 4.0 4.6 ns r set = 15k ? 4.6 5.5 6.3 ns r set = 50k ? 5.4 6.5 7.7 ns r set = 150k ? 7.5 8.3 9.3 ns t sk(o) output skew; note 2, 3 r set = 4k ? 125 260 ps r set = 15k ? 160 425 ps r set = 50k ? 200 525 ps r set = 150k ? 240 550 ps t sk(p) pulse skew r set = 4k ? 80 185 ps rset 4k ? 265 ps t sk(pp) part-to-part skew; note 3, 4 r set = 4k ? 600 1200 ps r set = 15k ? 825 1500 ps r set = 50k ? 975 2100 ps r set = 150k ? 1245 1650 ps t sl(o) output clock slew rate r set = 4k ? 0.450 0.650 1.3 v/ns r set = 15k ? 0.110 0.170 0.350 v/ns r set = 50k ? 0.110 0.150 0.325 v/ns r set = 150k ? 0.075 0.115 0.250 v/ns odc output duty cycle; note 5 r set = 4k ? , f ref 200mhz 45 50 55 % r set = 15k ? , f ref 30mhz 48 50 52 % r set = 50k ? , f ref 20mhz 48 50 52 % r set = 150k ? , f ref 16mhz 48 50 52 %
ics854110aki revision b january 27, 2011 6 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices oper ating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 5: input duty cycle must be 50%. t r / t f output rise/ fall time; 30% to 70% r set = 4k ? 100 300 500 ps r set = 15k ? 600 1030 1600 ps r set = 50k ? 650 1160 1850 ps r set = 150k ? 800 1540 2200 ps symbol parameter test conditio ns minimum typical maximum units
ics854110aki revision b january 27, 2011 7 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer additive phase jitter the spectral purity in a band at a s pecific offset from the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator used is, "rohde & schwarz sma 100a signal generator into a hp 8133a 3ghz pulse generator". additive phase jitter @ 125mhz 12khz to 20mhz = 0.291ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics854110aki revision b january 27, 2011 8 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer parameter measurement information 2.5v lvds output load ac test circuit output skew pulse skew differential input level part-to-part skew propagation delay scope qx nqx lvds 2.5v5% power supply +? float gnd v dd t sk(o) qx nqx qy nqy t plh t phl t sk(p) = |t phl - t plh | clk[0:1] nclk[0:1] qy nqy v dd nclk0, nclk1 clk0, clk1 gnd v cmr cross points v pp t sk(pp) part 1 part 2 qx nqx qy nqy t pd nq[0:9] q[0:9] nclk[0:1] clk[0:1]
ics854110aki revision b january 27, 2011 9 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer parameter measurement in formation, continued output rise/fall time differential output voltage setup differential output slew rate output duty cycle/pulse width/period offset voltage setup 30% 70% 70% 30% t r t f v od nq[0:9] q[0:9] ? ? ? 100 out out lvds dc input v od / ? v od v dd q ? nq t r t f v f v r -100mv +100mv +100mv -100mv 50% nq[0:9] q[0:9] t pw t period t pw t period odc = x 100% out out lvds dc input ? ? ? v os / ? v os v dd
ics854110aki revision b january 27, 2011 10 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds outputs should be terminated with 100 ? resistor between the differential pair.
ics854110aki revision b january 27, 2011 11 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer differential clock input interface the clk/nclk accepts lvpecl, lvds and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2c show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termi nation recommendation. please consult with the vendor of the driv er component to confirm the driver termination requirements. figure 2a. clk/nclk input driven by a 2.5v lvpecl driver figure 2c. clk/nclk input dr iven by an lvds driver figure 2b. clk/nclk input driven by a 2.5v lvpecl driver with ac coupler clk nclk differential input lvpecl 2.5v zo = 50 ? zo = 50 ? 2.5v r1 50 ? r2 50 ? r3 18 ? 2.5v r1 100 ? lvds clk nclk 2.5v differential input zo = 50 ? zo = 50 ? r1 125 r2 125 r5 100 - 200 r6 100 - 200 clk nclk 2.5v lvpecl 2.5v zo = 50 ? zo = 50 ? 2.5v differential input c1 c2 r3 84 r4 84 2.5v
ics854110aki revision b january 27, 2011 12 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb pr ovides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the groun d plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ? heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz cop per via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics854110aki revision b january 27, 2011 13 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer lvds driver termination a general lvds interface is shown in figure 4. standard termination for lvds type output stru cture requires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 4 can be used with either type of output structure. if using a non-standard termination, it is recommended to contact idt and conf irm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. figure 4. typical lvds driver termination 100 ? ? + 100 ? differential transmission line lvds driver lvds receiver
ics854110aki revision b january 27, 2011 14 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer power considerations this section provides information on power dissi pation and junction temperature for the ICS854110I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics54110i is the sum of the core power plus the power dissipation in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. total power dissipation, includes power dissipation on external components. p_core+load = v dd_max * i dd_core+load = 2.625v * 86ma = 225.75mw where: i dd_core+load is the total supply current which includes external components to calculate the power dissipation on the device alone, pd_total , and use it for junction temperat ure calculation, subtract the power dissipation on the external components. pd_total = p_core+load ? (p_load + p_rset) where: p_load is power dissipation on the output loadings p_rset is power dissipation on the r set the load current per output is: iout = (i dd_core+load ? i dd_no_load ) / n = (86ma ? 18ma) / 10 = 6.8ma where: i dd_no_load is i dd current at no load condition n is number of outputs power dissipation on output loads p_load = (iout)^2 * r_load * n = (6.8ma)^2 * 100 ? * 10 = 46.2mw power dissipation on r set p_rset = (vrset)^2 / r set = (1v)^2 / 4k ? = 0.25mw (note: p_rset is small and can be negligible) total power dissipation on the part excluding the power dissipation on the external components. pd_total = p_core+load ? (p_load + p_rset) = 225.75mw ? (46.2mw + 0.25mw) = 179.3mw
ics854110aki revision b january 27, 2011 15 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 65.7c/w per table 6a below. therefore, tj for an ambient temperatur e of 85c with all outputs switching is: 85c + 0.179w * 65.7c/w = 96.8c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6a. thermal resistance ja for 32 lead lqfp, forced convection table 6b. thermal resistance ja for 32 lead vfqfn, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 65.7c/w 55.9c/w 52.4c/w ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
ics854110aki revision b january 27, 2011 16 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer reliability information table 7a. ja vs. air flow table for a 32-lead vfqfn table 7b. ja vs. air flow table for a 32-lead lqfp transistor count the transistor count for ICS854110I is: 1757 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 37.0c/w 32.4c/w 29.0c/w ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 65.7c/w 55.9c/w 52.4c/w
ics854110aki revision b january 27, 2011 17 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer package outline and package dimensions package outline - k suffix for 32-lead vfqfn table 8a. package dimensions for 32-lead vfqfn reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8a. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.50
ics854110aki revision b january 27, 2011 18 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer package outline and package dimensions package outline - y suffix for 32-lead lqfp table 8b. package dimensions 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bba all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.30 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic e 0.80 basic l 0.45 0.60 0.75 0 7 ccc 0.10
ics854110aki revision b january 27, 2011 19 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer ordering information table 9. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configur ation and are rohs compliant. part/order number marking package shipping packaging temperature 854110akilf ics54110ail ?lead-free? 32 lead vfqfn tray -40 c to 85 c 854110akilft ics54110ail ?lead-free? 32 lead vfqfn 2500 tape & reel -40 c to 85 c 854110ayilf ics854110ail ?lead-free? 32 lead lqfp tray -40 c to 85 c 854110ayilft ics854110ail ?lead-free? 32 lead lqfp 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics854110aki revision b january 27, 2011 20 ?2011 integrated device technology, inc. ICS854110I data sheet 2.5v differential lvds clock buffer revision history sheet rev table page description of change date b t4a 4 power supply dc characteristics table - added i dd spec of 30ma max. 1/27/11
ICS854110I preliminary data sheet 2.5v differential lvds clock buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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